32k x 16 static ram cy7c1020bn cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06443 rev. ** revised february 1, 2006 features ?high speed ?t aa = 12, 15 ns ? cmos for optimum speed/power ? low active power ? 825 mw (max.) ? low cmos standby power (l version only) ? 2.75 mw (max.) ? automatic power-down when deselected ? independent control of upper and lower bits ? available in 44-pin tsop ii and 400-mil soj functional description the cy7c1020bn is a high-performance cmos static ram organized as 32,768 words by 16 bits. this device has an automatic power-down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 1 through i/o 8 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 9 through i/o 16 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 1 to i/o 8 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 9 to i/o 16 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 1 through i/o 16 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1020bn is available in standard 44-pin tsop type ii and 400-mil-wide soj packages. we logic block diagram pin configuration 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view soj / tsop ii 12 13 41 44 43 42 16 15 29 30 v cc a 15 a 14 a 13 a 12 nc nc a 3 oe v ss a 5 i/o 16 a 2 ce i/o 3 i/o 1 i/o 2 bhe nc a 1 a 0 18 17 20 19 i/o 4 27 28 25 26 22 21 23 24 nc v ss i/o 7 i/o 5 i/o 6 i/o 8 a 6 a 7 ble v cc i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 a 8 a 9 a 10 a 11 32k x 16 ram array i/o 1 ?i/o 8 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 sense amps data in drivers oe a 2 a 1 i/o 9 ?i/o 16 ce we ble bhe a 8
cy7c1020bn document #: 001-06443 rev. ** page 2 of 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [1] .... ?0.5v to +7.0v dc voltage applied to outputs in high z state [1] ......................................?0.5v to v cc +0.5v dc input voltage [1] ...................................?0.5v to v cc +0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma selection guide 7c1020bn-12 7c1020bn-15 maximum access time (ns) 12 15 maximum operating current (ma) 140 130 maximum cmos standby current (ma) 3 3 l 0.5 0.5 operating range range ambient temperature [2] v cc commercial 0c to +70c 5v 10% industrial ?40c to +85c 5v 10% electrical characteristics over the operating range parameter description test conditions 7c1020bn-12 7c1020bn-15 unit min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 6.0 2.2 6.0 v v il input low voltage [1] ?0.5 0.8 ?0.5 0.8 v i ix input load current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v i < v cc , output disabled ?1 +1 ?1 +1 a i os output short circuit current [3] v cc = max., v out = gnd ?300 ?300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 140 130 ma i sb1 automatic ce power-down current?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 20 20 ma i sb2 automatic ce power-down current?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 3 3 ma l 0.5 0.5 ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 8 pf c out output capacitance 8 pf notes: 1. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 2. t a is the case temperature. 3. not more than one output should be shorted at one time. du ration of the short circuit should not exceed 30 seconds. 4. tested initially and after any design or process changes that may affect these parameters.
cy7c1020bn document #: 001-06443 rev. ** page 3 of 8 ac test loads and waveforms switching characteristics [5] over the operating range parameter description 7c1020bn-12 7c1020bn-15 unit min. max. min. max. read cycle t rc read cycle time 12 15 ns t aa address to data valid 12 15 ns t oha data hold from address change 3 3 ns t ace ce low to data valid 12 15 ns t doe oe low to data valid 6 7 ns t lzoe oe low to low z [6] 0 0 ns t hzoe oe high to high z [6, 7] 6 7 ns t lzce ce low to low z [6] 3 3 ns t hzce ce high to high z [6, 7] 6 7 ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 12 15 ns t dbe byte enable to data valid 6 7 ns t lzbe byte enable to low z 0 0 ns t hzbe byte disable to high z 6 7 ns write cycle [8] t wc write cycle time 12 15 ns t sce ce low to write end 9 10 ns t aw address set-up to write end 8 10 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 8 10 ns t sd data set-up to write end 6 8 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [6] 3 3 ns t hzwe we low to high z [6, 7] 6 7 ns t bw byte enable to end of write 8 9 ns notes: 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 8. the internal write time of the memory is defined by the overlap of ce low, we low and bhe / ble low. ce , we and bhe / ble must be low to initiate a write, and the transition of these signals can terminate the write. the input data set-up and hold timing should be reference d to the leading edge of the signal that terminates the write. 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) output r 481 ? r 481 ? r2 255 ? r2 255 ? 167 equivalent to: thvenin equivalent 1.73v 30 pf rise time: 1 v/ns fall time: 1 v/ns
cy7c1020bn document #: 001-06443 rev. ** page 4 of 8 switching waveforms read cycle no. 1 [9, 10] read cycle no. 2 (oe controlled) [10, 11] notes: 9. device is continuously selected. oe , ce , bhe and/or bhe = v il . 10. we is high for read cycle. 11. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb
cy7c1020bn document #: 001-06443 rev. ** page 5 of 8 write cycle no. 1 (ce controlled) [12, 13] write cycle no. 2 (ble or bhe controlled) notes: 12. data i/o is high impedance if oe or bhe and/or ble = v ih . 13. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw data i/o address ce we bhe ,ble t t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce
cy7c1020bn document #: 001-06443 rev. ** page 6 of 8 write cycle no. 3 (we controlled, oe low) truth table ce oe we ble bhe i/o 1 ?i/o 8 i/o 9 ?i/o 16 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high z read ? lower bits only active (i cc ) h l high z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high z write ? lower bits only active (i cc ) h l high z data in write ? upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 12 cy7c1020bn-12vc 51-85082 44-lead (400-mil) molded soj commercial cy7c1020bn-12vxc 51-85082 44-lead (400 -mil) molded soj (pb-free) commercial cy7c1020bn-12zc 51-85087 44-pin tsop type ii commercial cy7c1020bn-12zxc 51-85087 44-pin tsop type ii (pb-free) commercial 15 cy7c1020bn-15zc 51-85087 44-pin tsop type ii commercial cy7c1020bn-15zxc 51-85087 44-pin tsop type ii (pb-free) commercial please contact local sales representative regarding availability of these parts. switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe
cy7c1020bn document #: 001-06443 rev. ** page 7 of 8 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams 51-85082-*b 44-lead (400-mil) molded soj (51-85082) 51-85087-*a 44-pin tsop ii (51-85087)
cy7c1020bn document #: 001-06443 rev. ** page 8 of 8 document history page document title: cy7c1020bn 32k x 16 static ram document #: 001-06443 rev. ecn no. issue date orig. of change description of change ** 426812 see ecn nxr new data sheet
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